BLOCK DIAGRAM OF 8254 :
DATA BUS BUFFER
This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus.
READ/WRITE LOGIC
The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 8254. A1 and A0 select one of the three counters or the Control Word Register to be read from/written into. A ``low'' on the RD in put tells the 8254 that the CPU is reading one of the counters. A ``low'' on the WR input tells the 8254 that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS;RD and WR are ignored unless the 8254 has been selected by holding CS low.
CONTROL WORD REGISTER
The Control Word Register (see Figure 4) is selected by the Read/Write Logic when A1, A0 e11. If the CPU then does a write operation to the 8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters. The Control Word Register can only be written to;status information is available with the Read Back n Command.
COUNTER 0, COUNTER 1, COUNTER 2
These three functional blocks are identical in operation,so only a single Counter will be described. The Counters are fully independent. Each Counter may operate in a different Mode.The Control Word Register is shown in the figure; it is not part of the Counter itself, but its contents deter mine how the Counter operates when latched, contains the current contents of the Control Word Register and status of the output and null count flag. (See detailed explanation of the Read Back command.)
The actual counter is labelled CE (for ``Counting Element'').It is a 16-bit preset table synchronous down counter. OLM and OLL are two 8-bit latches. OL stands for``Output Latch''; the subscripts M and L stand for ``Most significant byte'' and ``Least significant byte''respectively. Both are normally referred to as one unit and called just OL. These latches normally ``follow''the CE, but if a suitable Counter Latch Command is sent to the 8254, the latches ``latch'' the present count until read by the CPU and then return to ``following'' the CE. One latch at a time is enabled by the counter's Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE it self cannot be read; whenever you read the count, it is the OL that is being read. Similarly, there are two 8-bit registers called CRM and CRL (for ``Count Register''). Both are normally referred to as one unit and called just CR. When anew count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRL are cleared when the Counter is programmed. In this way, if the Counter has been programmed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero.Note that the CE cannot be written into; whenever a count is written, it is written into the CR.The Control Logic is also shown in the diagram. CLK n, GATE n, and OUT n are all connected to the outside world through the Control Logic.
